For example, Japanese Unexamined Patent Application Publication JP 1989-59173 A describes a two-port memory test pattern generator provided with two pairs of a timing signal generator for a two-port memory and a pattern generator. According to this configuration, for example, when carrying out a test for addresses 0 to 11, at first one of two pairs of the timing signal generator and the pattern generator carries out a write operation to addresses 0 and 11 with respect to the port A. At that time, upon ending the write operation in address 5 located halfway among the target addresses, a start signal is issued to the other pair, thereby the pair executes a read operation from addresses 0 to 5 with respect to the port B. Consequently, the write operation in addresses 6 to 11 with respect to the port A and the read operation from addresses 0 to 5 with respect to the read operation can be executed simultaneously with use of different clock frequencies, respectively. Thus the tests can be carried out asynchronously.